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PCF8574P 데이터시트(PDF) 11 Page - NXP Semiconductors |
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PCF8574P 데이터시트(HTML) 11 Page - NXP Semiconductors |
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11 / 24 page ![]() 1997 Apr 02 11 Philips Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 7.2 Interrupt (see Figs 12 and 13) The PCF8574 provides an open drain output (INT) which can be fed to a corresponding input of the microcontroller. This gives these chips a type of master function which can initiate an action elsewhere in the system. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv the signal INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from or written to the port which has generated the interrupt. Resetting occurs as follows: • In the READ mode at the acknowledge bit after the rising edge of the SCL signal • In the WRITE mode at the acknowledge bit after the HIGH-to-LOW transition of the SCL signal • Interrupts which occur during the acknowledge clock pulse may be lost (or very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting will be detected and, after the next rising clock edge, will be transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit. 7.3 Quasi-bidirectional I/Os (see Fig.14) A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. handbook, full pagewidth MBD976 MICROCOMPUTER INT INT INT PCF8574 (1) PCF8574 (2) V DD INT PCF8574 (16) Fig.12 Application of multiple PCF8574s with interrupt. Fig.13 Interrupt generated by a change of input to I/O P5. handbook, full pagewidth MBD972 S 0 1 0 0 A2 A1 A0 1 A start condition 1 P5 R/W acknowledge from slave 1 SDA SCL DATA INTO P5 t ir INT slave address (PCF8574) data from port 1 234 567 8 P stop condition t iv |
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