PCF8578USLASH2 datasheet(28/44 Pages) PHILIPS

28 / 44 page

1998 Sep 08

Philips Semiconductors

Product speciﬁcation

LCD row/column driver for dot matrix

graphic displays

PCF8578

13 AC CHARACTERISTICS

All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD.

VDD = 2.5 to 6 V; VSS =0V; VLCD =VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fCLK1

clock frequency at multiplex rates of

1 : 8, 1 : 16 and 1 : 32

ROSC = 330 kΩ; VDD = 6 V

1.2

2.1

3.3

kHz

fCLK2

clock frequency at multiplex rates of

1:24

ROSC = 330 kΩ; VDD = 6 V

0.9

1.6

2.5

kHz

tPSYNC

SYNC propagation delay

−−

500

tPLCD

driver delays

VDD − VLCD =9V;

with test loads

−−

100

µs

I2C-bus

fSCL

SCL clock frequency

−−

100

kHz

tSW

tolerable spike width on bus

−−

100

tBUF

bus free time

4.7

−−µs

tSU;STA

start condition set-up time

repeated start codes only

4.7

−−µs

tHD;STA

start condition hold time

4.0

−µs

tLOW

SCL LOW time

4.7

−−µs

tHIGH

SCL HIGH time

4.0

−−µs

SCL and SDA rise time

−−

µs

SCL and SDA fall time

−−

0.3

µs

tSU;DAT

data set-up time

250

−−

tHD;DAT

data hold time

−−

tSU;STO

stop condition set-up time

4.0

−−µs

Fig.19 AC test loads.

MSA829

Ω

3.3 k

Ω

1.5 k

0.5 VDD

VDD

SDA

SYNC, CLK

1 nF

C39 to C32,

R31/C31 to R8/C8

and R7 to R0

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