13

AT25FS010

5167B–SFLSH–1/07

RDSR. The AT25FS010 will automatically return to the write disable state at the comple-

tion of the CHIP ERASE cycle.

Timing Diagrams (for SPI Mode 0 (0, 0))

Figure 3. Synchronous Data Timing

Figure 4. WREN Timing

Figure 5. WRDI Timing

V

OH

V

OL

HI-Z

HI-Z

t V

VALID IN

V

IH

V

IL

tH

t

SU

t DIS

V

IH

V

IL

t WH

t CSH

V

IH

V

IL

t CSS

t CS

t WL

t HO

CS

SCK

SI

SO

0

1

2

3

4

5

6

7

HI-Z

WREN OP-CODE

CS

SCK

SI

SO

HI-Z

WRDI OP-CODE

CS

SCK

SI

SO