PCK2001MDB datasheet(11/13 Pages) PHILIPS

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Philips Semiconductors

Product specification

PCK2001M

14.318–150 MHz I2C 1:10 Clock Buffer

1999 Jul 06

AC WAVEFORMS

VM = 1.5V

VX = VOL + 0.3V

VY = VOH –0.3V

VOL and VOH are the typical output voltage drop that occur with the

output load.

BUF_IN

INPUT

tPLH

tPHL

BUF_OUT

SW00246

VDD

Figure 1. Load circuitry for switching times.

tPLZ

tPZL

nOE INPUT

GND

VDD

OUTPUT

LOW-to-OFF

OFF-to-LOW

VOL

VOH

OUTPUT

HIGH-to-OFF

OFF-to-HIGH

VSS

outputs

enabled

outputs

enabled

outputs

disabled

tPHZ

tPZH

SW00245

VDD

Figure 2. 3-State enable and disable times

DUTY CYCLE

TSDKP

TSDKH

TSDRISE

TSDFALL

TSDKL

2.4

1.5

0.4

SW00247

Figure 3. SDRAM Output clock

DUTY CYCLE

tkp

tkh

tkl

2.4

1.5

0.4

SW00479

Figure 4. Buffer Output clock

TEST CIRCUIT

PULSE

GENERATOR

D.U.T.

VDD

TEST

tPLH/tPHL

Open

tPLZ/tPZL

<VDD

tPHZ/tPZH

VSS

Open

VSS

<VDD

500

Ω

500

Ω

SW00251

Figure 5. Load circuitry for switching times

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