Philips Semiconductors

Product specification

PCK953

50–125 MHz PECL input/CMOS output

3.3 V PLL clock driver

2001 Feb 08

6

At the load end, the voltage will double due to the near unity

reflection coefficient, to 2.62 V. It will then increment towards the

quiescent 3.0 V in steps separated by one round-trip delay (in this

case 4.0 ns).

SW00630

OutB

3.0

2.5

2.0

1.5

1.0

0.5

0

TIME (ns)

2

4

6

8

10

12

14

In

OutA

Figure 3. Single versus dual waveforms

Since this step is well above the threshold region, it will not cause

any false clock triggering, however designers may be uncomfortable

with unwanted reflections on the line. To better match the

impedances when driving multiple lines, the situation in Figure 4

should be used. In this case, the series terminating resistors are

reduced such that when the parallel combination is added to the

output buffer impedance, the line impedance is perfectly matched.

SW00629

PCK953

14

Ω

OUTPUT

BUFFER

14

Ω + 22 Ω ø 22 Ω = 50 Ω ø 50 Ω

25

Ω = 25 Ω

Figure 4. Optimized dual line termination

SPICE level output buffer models are available for engineers who

want to simulate their specific interconnect schemes. In addition, IV

characteristics are in the process of being generated to support the

other board-level simulators in general use.