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PDIUSBH11AD 데이터시트(PDF) 20 Page - NXP Semiconductors

부품명 PDIUSBH11AD
상세설명  Universal Serial Bus Hub
PDF  28 Pages
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PDIUSBH11AD 데이터시트(HTML) 20 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
PDIUSBH11A
Universal Serial Bus Hub
1999 Jul 22
20
AC CHARACTERISTICS (AI/O pins, FULL speed)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Driver characteristics
CL = 50 pF;
Rpu = 1.5 kΩ on D+ to VCC
Transition Time:
Between 10% and 90%
tR
Rise time
4
20
ns
tF
Fall time
4
20
ns
tRFM
Rise/fall time matching
(tR/tF)
90
110
%
VCRS
Output signal crossover voltage
1.3
2.0
V
Driver Timings
tEOPT
Source EOP width
Figure 1
160
175
ns
tDEOP
Differential data to EOP transition skew
Figure 1
–2
5
ns
Receiver Timings
Receiver Data Jitter Tolerance
Characterized and not tested
tJR1
To next transition
Characterized and not tested.
Guaranteed by design.
–18.5
18.5
ns
tJR2
For paired transitions
Guaranteed by design.
–9
9
ns
EOP Width at Receiver
tEOPR1
Must reject as EOP
Figure 1
40
ns
tEOPR2
Must accept
82
ns
Hub Timings
Full Speed downstream port
tHDD
Hub Differential Data Delay
Figure 2
40
tSOP
Data bit width distortion after SOP
Figure 2
–5
3
ns
tEOPDR
Hub EOP Delay Relative to tHDD
Figure 3
0
15
ns
tHESK
Hub EOP Output Width Skew
Figure 3
–15
+15
AC CHARACTERISTICS (AI/O pins, LOW speed)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Driver characteristics
CL = 50 pF and 350 pF;
Rpu = 1.5 kΩ on D– to VCC
Transition Time:
Between 10% and 90%
tLR
Rise time
CL = 50 pF
75
ns
tLR
Rise time
CL = 350 pF
300
ns
tLF
Fall time
CL = 50 pF
75
ns
tLF
Fall time
CL = 350 pF
300
ns
tRFM
Rise/fall time matching
(tR/tF)
80
120
%
VLCRS
Output signal crossover voltage
1.3
2.0
V
Driver Timings
tLEOPT
Source EOP width
Figure 1
1.25
1.50
µs
tLDEOP
Differential data to EOP transition skew
Figure 1
–40
100
ns
Receiver Timings
EOP Width at Receiver
Figure 1
tLEOPR1
Must reject as EOP
330
ns
tLEOPR2
Must accept
675
ns
Hub Timings
Low Speed downstream port
tLHDD
Hub Differential Data Delay
Figure 2
300
tLSOP
Data bit width distortion after SOP
Figure 2
–65
45
ns
tLEOPDR
Hub EOP Delay Relative to tLHDD
Figure 3
0
200
ns
tLHESK
Hub EOP Output Width Skew
Figure 3
–300
+300



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