TCS34713FN datasheet(17/39 Pages) OSRAM

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Page 16

ams Datasheet

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[v1-01] 2018-Mar-27

State Diagram

Figure 20 shows a more detailed flow for the state machine. The

device starts in the sleep mode. The PON bit is written to enable

the device. A 2.4ms delay will occur before entering the start

state. If the WEN bit is set, the state machine will cycle through

the wait state. If the WLONG bit is set, the wait cycles are

extended by 12× over normal operation. When the wait counter

terminates, the state machine will step to the RGBC state.

The AEN should always be set. In this case, a minimum of 1

integration time step should be programmed. The RGBC state

machine will continue until it reaches the terminal count, at

which point the data will be latched in the RGBC register and

the interrupt set, if enabled.

Figure 20:

Expanded State Diagram

Wait

Check

PON = 1

PON = 0

Sleep

ALS

Check

Wait

Start

WEN = 1

ALS

Delay

AEN = 1

1 to 256steps

Step: 2.4 ms

Time: 2.4 ms − 614 ms

WLONG = 0

1 to 256 steps

Step: 2.4 ms

Time: 2.4 ms − 614 ms

Minimum − 2.4 ms

WLONG = 1

1 to 256 steps

Step: 29 ms

Time: 29 ms − 7.4 s

Minimum − 29 ms

Time: 2.4 ms

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