TCS37717FN datasheet(30/49 Pages) OSRAM

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ams Datasheet

Page 29

[v1-31] 2018-Apr-04

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TCS3771 − Principles of Operation

Wait Time Register (0x03)

Wait time is set 2.4ms increments unless the WLONG bit is

asserted in which case the wait times are 12× longer. WTIME is

programmed as a 2’s complement number.

Figure 33:

Wait Time Register

RGBC Interrupt Threshold Registers

(0x04 − 0x07)

The RGBC Interrupt Threshold Registers provides the values to

be used as the high and low trigger points for the comparison

function for interrupt generation. If the value generated by the

clear channel crosses below the lower threshold specified, or

above the higher threshold, an interrupt is asserted on the

interrupt pin.

Figure 34:

RGBC Interrupt Threshold Registers

Field

Bits

Description

WTIME

7:0

Wait Time

Time

(WLONG = 0)

Time

(WLONG = 1)

0xFF

2.4ms

0.029 sec

0xAB

204ms

2.45 sec

0x00

256

614ms

7.4 sec

Address

Bits

Description

AILTL

0x04

7:0

RGBC clear channel low threshold lower byte

AILTH

0x05

7:0

RGBC clear channel low threshold upper byte

AIHTL

0x06

7:0

RGBC clear channel high threshold lower byte

AIHTH

0x07

7:0

RGBC clear channel high threshold upper byte

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