TSL25213 datasheet(17/81 Pages) OSRAM

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[v3-00] 2022-Dec-21

TSL2521 − Detailed Description

I²C Protocol

The device uses I²C serial communication protocol for

communication. The device supports 7-bit chip addressing and

both standard and full-speed clock frequency modes. Read and

Write transactions comply with the standard set by Philips (now

NXP). For a complete description of the I²C protocol, please

review the NXP I²C design specification.

Internal to the device, an 8-bit buffer stores the register address

location of the desired byte to read or write. This buffer

auto-increments upon each byte transfer and is retained

between transaction events (I.e. valid even after the master

issues a STOP command and the I²C bus is released). During

consecutive Read transactions, the future/repeated I²C Read

transaction may omit the memory address byte normally

following the chip address byte; the buffer retains the last

All 16-bit fields have a latching scheme for reading and writing.

In general it is recommended to use I²C bursts whenever

possible, especially in this case when accessing two bytes of

one logical entity. When reading these fields, the low byte must

be read first, and it triggers a 16-bit latch that stores the 16-bit

field. The high byte must be read immediately afterwards. When

writing to these fields, the low byte must be written first,

immediately followed by the high byte. Reading or writing to

these registers without following these requirements will cause

errors.

A Write transaction consists of a START, CHIP-ADDRESSWRITE,

each byte (9th clock pulse) the slave places an

ACKNOWLEDGE/NOT- ACKNOWLEDGE (ACK/NACK) on the bus.

If NACK is transmitted by the slave, the master may issue a STOP.

A Read transaction consists of a START, CHIP-ADDRESSWRITE,

BYTE(S), and STOP. Following all but the final byte the master

places an ACK on the bus (9th clock pulse). Termination of the

Read transaction is indicated by a NACK being placed on the

bus by the master, followed by STOP.

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