TSL2580CS datasheet(29/53 Pages) OSRAM

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[v1-00] 2016-Apr-05

TSL2580, TSL2581 − Register Set

Constant (13h)

The CONSTANT register provides a means to facilitate SMBus

block transfers that is used as the Byte Count in the SMBus

protocol. For example, all four ADC Channel Data Registers can

be read in a single SMBus block transfer if an SMBus Block Read

is initiate at address 13h. This register defaults to the constant

4, but may be set to other values depending upon the end

application. For example, if manual integration is employed and

the register is set to 5, then all four ADC Channel Data Registers

and the Manual Integration Timer Register can be read in a

single SMBus read block transaction.

Figure 36:

Constant Register

ADC Channel Data Registers (14h - 17h)

The ADC channel data are expressed as 16-bit values spread

across two registers. The ADC channel 0 data registers,

DATA0LOW and DATA0HIGH provide the lower and upper bytes,

respectively, of the ADC value of channel 0. Registers

DATA1LOW and DATA1HIGH provide the lower and upper bytes,

respectively, of the ADC value of channel 1. All channel data

registers are read-only and default to 00h on power up.

Figure 37:

ADC Channel Data Registers

CONSTANT

Field

Bits

Description

CONSTANT

7:0

Constant value used as the byte count for SMBus block read/write transactions. I²C

protocol does not use the byte count field in the block transaction, so this register

should be ignored if an TSL2581 device is used.

Address

Bits

Description

DATA0LOW

14h

7:0

ADC channel 0 lower byte

DATA0HIGH

15h

7:0

ADC channel 0 upper byte

DATA1LOW

16h

7:0

ADC channel 1 lower byte

DATA1HIGH

17h

7:0

ADC channel 1 upper byte

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