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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TSL25911FN 데이터시트(PDF) 22 Page - OSRAM GmbH |
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TSL25911FN 데이터시트(HTML) 22 Page - OSRAM GmbH |
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22 / 34 page  Datasheet, Public Page 21 [v3-00] 2023-Feb-08 Document Feedback TSL2591 − Register Description ALS data is stored as two 16-bit values; one for each channel. When the lower byte of either channel is read, the upper byte of the same channel is latched into a shadow register. The shadow register ensures that both bytes are the result of the same ALS integration cycle, even if additional integration cycles occur between the lower byte and upper byte register readings. Each channel independently operates the upper byte shadow register. So to minimize the potential for skew between CH0 and CH1 data, it is recommended to read all four ADC bytes in sequence. Register Address Bits Description C0DATAL 0x14 7:0 ALS CH0 data low byte C0DATAH 0x15 7:0 ALS CH0 data high byte C1DATAL 0x16 7:0 ALS CH1 data low byte C1DATAH 0x17 7:0 ALS CH1 data high byte ALS Data Register (0x14 - 0x17) |
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