TSL2772 datasheet(35/58 Pages) OSRAM

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[v2-00] 2023-Mar-30

TSL2772 − Principles O f Operation

Wait Time Register (0x03)

Wait time is set 2.73 ms increments unless the WLONG bit is

asserted in which case the wait times are 12x longer. WTIME is

programmed as a 2’s complement number. Upon power up, the

wait time register is set to 0xFF.

Figure 35:

Wait Time Register

Note(s):

1. The Proximity Wait Time Register should be configured before PEN and/or AEN is/are asserted.

ALS Interrupt Threshold Registers (0x04 - 0x07)

The ALS interrupt threshold registers provides the values to be

used as the high and low trigger points for the comparison

function for interrupt generation. If C0DATA crosses below the

low threshold specified, or above the higher threshold, an

interrupt is asserted on the interrupt pin.

Figure 36:

ALS Interrupt Threshold Registers

Field

Bits

Description

WTIME

7:0

WAIT TIME

TIME (WLONG = 0)

TIME (WLONG = 1)

0xFF

2.73ms

0.033s

0xB6

202ms

2.4s

0x00

256

699ms

8.4s

Address

Bits

Description

AILTL

0x04

7:0

ALS low threshold lower byte

AILTH

0x05

7:0

ALS low threshold upper byte

AIHTL

0x06

7:0

ALS high threshold lower byte

AIHTH

0x07

7:0

ALS high threshold upper byte

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