TSL26721 datasheet(23/47 Pages) OSRAM

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[v1-01] 2019-Nov-20

TSL2672 − Principles O f Operation

Figure 25:

Average IDD Current

I²C Protocol

Interface and control are accomplished through an I²C serial

compatible interface (standard or fast mode) to a set of registers

that provide access to device control functions and output data.

The devices support the 7-bit I²C addressing protocol.

The I²C standard provides for three types of bus transaction:

read, write, and a combined protocol (Figure 26). During a write

operation, the first byte written is a command byte followed by

data. In a combined protocol, the first byte written is the

command byte followed by reading a series of bytes. If a read

command is issued, the register address from the previous

command will be used for data access. Likewise, if the MSB of

the command is not set, the device will write a series of bytes

at the address stored in the last valid command with a register

address. The command byte contains either control information

or a 5-bit register address. The control commands can also be

used to clear interrupts.

The I²C bus protocol was developed by Philips (now NXP). For

a complete description of the I²C protocol, please review the

NXP I²C design specification at

http://www.i2c-bus.org/references/.

WEN

WTIME

WLONG

WAIT State

Average I

DD Current

n/a

0 ms

622

μA

0xFF

2.73 ms

490

μA

0xEE

49.2 ms

167

μA

0x00

699 ms

μA

0x00

8389 ms

μA

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