33742 datasheet(49/65 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33742

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Figure 30. HS Operation When Cyclic Sense Is Selected

LOW POWER CONTROL REGISTER (LPC)

Tables 35 through 39 contain the Low Power Control Register information. The LPC register controls:

• The state of HS in Stop and Sleep modes (HS permanently OFF or HS cyclic).

• Enable or disable of the forced wake-up function (SBC automatic wake-up after time spent in Sleep or Stop modes; time is

defined by the TIM2 sub register).

• Enable or disable the sense of the wake-up inputs (Lx) at the sampling point of the Cyclic Sense period (LX2HS bit). (Refer to

Reset Control Register (RCR) on page 44 for details of the LPC register setup required for proper cyclic sense or direct wake-

up operation.

The LPC register also reports the CANH and RXD diagnostic.

Cyclic Sense Timing, OFF Time

time

Sample

µs

HS OFF

HS ON

Lx Sampling Point

Cyclic Sense Timing,

ON Time

Table 34. TIM2 Control Bits

CSP2

CSP1

CSP0

Cyclic Sense Timing (ms)

Parameter

4.6

Cyclic Sense/FWU Timing 1

9.25

Cyclic Sense/FWU Timing 2

18.5

Cyclic Sense/FWU Timing 3

Cyclic Sense/FWU Timing 4

Cyclic Sense/FWU Timing 5

95.5

Cyclic Sense/FWU Timing 6

191

Cyclic Sense/FWU Timing 7

388

Cyclic Sense/FWU Timing 8

Table 35. Low Power Control Register

LPC

R/W

$110b

LX2HS

FWU

CAN-INT

HSAUTO

CANH2VDD

CANH2BAT

CANH2GND

RXPR

Reset Value

–

Reset Condition

(Write) (62)

–

POR, NR2R, N2R,

STB2R, STO2R

POR, NR2R, N2R,

STB2R, STO2R

POR, NR2R, N2R,

STB2R, STO2R

POR, NR2R, N2R,

STB2R, STO2R

Notes

62.

See Table 13, page 42, for definitions of reset conditions.

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