SN54LVTH16500, SN74LVTH16500

3.3V ABT 18BIT UNIVERSAL BUS TRANSCEIVERS

WITH 3STATE OUTPUTS

SCBS701F − JULY 1997 − REVISED SEPTEMBER 2003

3

POST OFFICE BOX 655303

FUNCTION TABLE†

INPUTS

OUTPUT

OEAB

LEAB

CLKAB

A

OUTPUT

B

L

X

X

X

Z

H

HX

L

L

H

HX

H

H

H

L

↓

LL

H

L

↓

HH

H

LH

X

B0‡

H

L

L

X

B0§

† A-to-B data flow is shown: B-to-A flow is similar, but

uses OEBA, LEBA, and CLKBA.

‡ Output level before the indicated steady-state input

conditions were established

§ Output level before the indicated steady-state input

conditions were established, provided that CLKAB

was low before LEAB went low

logic diagram (positive logic)

1D

C1

CLK

1D

C1

CLK

B1

OEAB

CLKAB

LEAB

LEBA

CLKBA

OEBA

A1

1

55

2

28

30

27

3

54

To 17 Other Channels

Pin numbers shown are for the DGG, DL, and WD packages.