전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AD5522JSVD 데이터시트(PDF) 29 Page - Analog Devices

부품명 AD5522JSVD
상세설명  Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
PDF  48 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD5522JSVD 데이터시트(HTML) 29 Page - Analog Devices

Back Button AD5522JSVD Datasheet HTML 25Page - Analog Devices AD5522JSVD Datasheet HTML 26Page - Analog Devices AD5522JSVD Datasheet HTML 27Page - Analog Devices AD5522JSVD Datasheet HTML 28Page - Analog Devices AD5522JSVD Datasheet HTML 29Page - Analog Devices AD5522JSVD Datasheet HTML 30Page - Analog Devices AD5522JSVD Datasheet HTML 31Page - Analog Devices AD5522JSVD Datasheet HTML 32Page - Analog Devices AD5522JSVD Datasheet HTML 33Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 29 / 48 page
background image
Preliminary Technical Data
AD5522
Rev. PrM | Page 29 of 48
Table 12. BUSY Pulse Width
Action
BUSY Pulse Width
(
μs max)
Loading data to PMU, System Control
Register or Readback
0.27
Loading x1 to any 1 PMU DAC Channel
1.25
Loading x1 to any 2 PMU DAC Channels
1.75
Loading x1 to any 3 PMU DAC Channels
2.25
Loading x1 to any 4 PMU DAC Channels
2.75
BUSY Pulse Width = ((Number of channels +1) × 500ns) + 250ns
BUSY also goes low during power-on reset and when a falling
edge is detected on the RESET pin.
WRITE
#1
1st
STAGE
2nd
STAGE
3rd
STAGE
~600ns
500ns
500ns
250ns
Calibration Engine Time
e.g. WRITE TO
3 FIN DAC REGISTERS
1st
STAGE
2nd
STAGE
3rd
STAGE
1st
STAGE
2nd
STAGE
3rd
STAGE
1st
STAGE
2nd
STAGE
3rd
STAGE
WRITE
#2
Figure 26. Multiple writes to DAC x1 registers
Writing data to the System control register, PMU control
register, m or c registers do not involve the digital calibration
engine, thus speeding up configuration of the device on power
on.
REGISTER UPDATE RATES
As mentioned previously the value of the X2 register is
calculated each time the user writes new data to the
corresponding X1 register. The calculation is performed by a
three stage process. The first two stages take 500ns each and the
third stage takes 250ns. When the writes to one of the X1
registers is complete the calculation process begins. If the write
operation involves the update of a single DAC channel the user
is free to write to another register provided that the write
operation doesn’t finish until the first stage calculation is
complete, i.e. 500ns after the completion of the first write
operation.
~600ns
500ns
500ns
250ns
Calibration Engine Time
1st
STAGE
2nd
STAGE
3rd
STAGE
WRITE
#1
1st
STAGE
2nd
STAGE
3rd
STAGE
WRITE
#2
1st
STAGE
2nd
STAGE
3rd
STAGE
WRITE
#3
Figure 27. Multiple Single Channel writes engaging calibration engine



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com