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IA82527-PLC44A-R 데이터시트(PDF) 10 Page - InnovASIC, Inc

부품명 IA82527-PLC44A-R
상세설명  Serial Communications Controller CAN Protocol
PDF  45 Pages
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제조업체  INNOVASIC [InnovASIC, Inc]
홈페이지  http://www.innovasic.com
Logo INNOVASIC - InnovASIC, Inc

IA82527-PLC44A-R 데이터시트(HTML) 10 Page - InnovASIC, Inc

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IA82527
04 May 2007
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
Copyright 
 2007
EN21070504-00
www.Innovasic.com
Customer Support:
Page 10 of 45
1-888-824-4184
©
2.2
Pin/Signal Descriptions
Descriptions of the pin and signal functions for the IA82527 Serial Communications Controller
are provided in Table 3.
Several of the IA82527 pins have different functions depending on the operating mode of the
device. Each of the different signals supported by a pin is listed and defined in Table 3, indexed
alphabetically in the first column of the table. Additionally, the name of the pin associated with
the signal as well as the pin numbers for both the PLCC and QFP packages are provided in the
“Pin” column. If the signal and pin names are the same, no entry is provided in the “Pin-Name”
column.
Table 3. IA82527 Pin/Signal Descriptions
Pin
Signal
Name
PLCC
QFP
Description
a0
a0/ad0/icp
4
42
a1
a1/ad1/cp
3
41
a2
a2/ad2/csas
2
40
a3
a3/ad3/ste
43
37
a4
a4/ad4/mosi
42
36
a5
a5/ad5
41
35
a6
a6/ad6/sclk
40
34
a7
a7/ad7
39
33
address bits 7–0. Input. Mode 3.
When the IA82527 is configured to operate in the 8-bit non-
multiplexed non-Intel
® architecture mode (Mode 3), these lines
provide the 8-bit address bus input to the device.
ad0
a0/ad0/icp
4
42
ad1
a1/ad1/cp
3
41
ad2
a2/ad2/csas
2
40
ad3
a3/ad3/ste
43
37
ad4
a4/ad4/mosi
42
36
ad5
a5/ad5
41
35
ad6
a6/ad6/sclk
40
34
ad7
a7/ad7
39
33
ad8
ad8/d0/p1.0
38
32
ad9
ad9/d1/p1.1
37
31
ad10
ad10/d2/p1.2
36
30
ad11
ad11/d3/p1.3
35
29
ad12
ad12/d4/p1.4
34
28
ad13
ad13/d5/p1.5
33
27
ad14
ad14/d6/p1.6
32
26
ad15
ad15/d7/p1.7
31
25
address/data bits 15–0. Input/Output. Mode 1.
When the IA82527 is configured to operate in the 16-bit multiplexed
Intel
® architecture mode (Mode 1), these lines provide the 16-bit
address bus (input) and the 16-bit data bus (input/output) for the
device.
ale
ale/as
5
43
address latch enable. Input. Active High. Mode 0 and Mode 1.
When the IA82527 is configured to operate in either the 8-bit
multiplexed Intel
® architecture mode (Mode 0) or the 16-bit
multiplexed Intel
® architecture mode (Mode 1), this signal latches the
address into the device during the address phase of the bus cycle.
continued
. . .



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