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ENTER REGISTER READ-BACK MODE

T0044-02

0

0

1

1

1

1

1

1

2

26

27

28

SDATA

FOUT

EnterRegister

Read-BackMode

Fetch

EEPROM

ContentWith

1 CLK

st

EEPROMContent

1 Bit Available After

1 FallingEdge

st

st

30 FallingEdge

SwitchesBackInto

NormalOperation

th

OutputOscillation

OutputOscillation

CDCE401

SCAS820 – JUNE 2006

Similar to the enter registerprogramming mode sequence, the enter register read-back mode is written into

SDATA. Before the enter register read-back mode is written, the device must be disabled via EN for 100

µs to

ensure that the EEPROM content is read out correctly with enter register read-back mode. After the command

has been issued, the SDATA input is reconfigured as a clock input. By applying one clock, the EEPROM content

is read into shift registers. Now, by further applying clocks at SDATA, the EEPROM content can be clocked out

and observed at FOUT. Also, FOUT is reconfigured during that operation, as can be seen in the following figure.

normal operation.

Figure 4. Typical Register Read-Back Cycle

In Table 4, the content of the bits in the output stream is summarized. Note that the MSB is clocked out first.

Table 4. Read-Back Cycle Bit Stream

OUTPUT-STREAM BITS

FUNCTION

Bits[0:2]

Revision identifier (MSB first)

Bit[3]

EEPROM status:

0 = EEPROM has never been written.

1 = EEPROM has been programmed before.

Bit[4]

EEPROM lock:

0 = EEPROM can be rewritten.

1 = EEPROM is locked; rewriting to the EEPROM is not possible.

Bits[5:12]

Storage value, word2 (MSB first)

Bits[13:20]

Storage value, word1 (MSB first)

Bits[21:28]

Storage value, word0 (MSB first)

8

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