56F807 datasheet(13/60 Pages) FREESCALE

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GPIO Signals

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

2.6 GPIO Signals

RSTO

Output

Reset Output—This output reflects the internal reset state of the

chip.

RESET

Input

(Schmitt)

Input

Reset—This input is a direct hardware reset on the processor. When

RESET is asserted low, the device is initialized and placed in the

Reset state. A Schmitt trigger input is used for noise immunity. When

the RESET pin is deasserted, the initial chip operating mode is

latched from the EXTBOOT pin. The internal reset signal will be

deasserted synchronous with the internal clocks, after a fixed number

of internal clocks.

To ensure complete hardware reset, RESET and TRST should be

asserted together. The only exception occurs in a debugging

environment when a hardware device reset is required and it is

necessary not to reset the OnCE/JTAG module. In this case, assert

RESET, but do not assert TRST.

EXTBOOT

Input

(Schmitt)

Input

External Boot—This input is tied to VDD to force device to boot from

off-chip memory. Otherwise, it is tied to VSS.

Table 2-10 Dedicated General Purpose Input/Output (GPIO) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

GPIOB0-

GPIOB7

Input

Output

Input

Port B GPIO—These eight pins are dedicated General Purpose I/O

(GPIO) pins that can individually be programmed as input or output

pins.

After reset, the default state is GPIO input.

GPIOD0-

GPIOD5

Input

Output

Input

Port D GPIO—These six pins are dedicated GPIO pins that can

individually be programmed as an input or output pins.

After reset, the default state is GPIO input.

Table 2-9 Interrupt and Program Control Signals (Continued)

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

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