DSP56364P datasheet(21/148 Pages) FREESCALE

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External Clock Operation

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-5

3.7

External Clock Operation

The DSP56364 system clock is an externally supplied square wave voltage source connected to EXTAL

(See Figure 3-1).

Figure 3-1 External Clock Timing

Internal clock low period

• With PLL disabled

—

ETC

—

• With PLL enabled and MF

≤ 4

0.49

× ET

C ×

PDF

× DF/MF

—0.51

× ET

C ×

PDF

× DF/MF

• With PLL enabled and MF > 4

0.47

× ET

C ×

PDF

× DF/MF

—0.53

× ET

C ×

PDF

× DF/MF

Internal clock cycle time with PLL enabled

—ETC × PDF ×

DF/MF

—

Internal clock cycle time with PLL disabled

—2

× ET

—

Instruction cycle time

ICYC

—TC

—

1 DF = Division Factor

Ef = External frequency

ETC = External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

TC = internal clock cycle

2 See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL.

Table 3-4 Internal Clocks (continued)

Characteristics

Symbol

Expression1, 2

Min

Typ

Max

EXTAL

VILC

VIHC

Midpoint

Note: The midpoint is 0.5 (VIHC + VILC).

ETH

ETL

ETC

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