DSP56366 datasheet(51/110 Pages) FREESCALE

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DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-25

Figure 3-14 DRAM Out-of-Page Wait States Selection Guide

Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2

No.

Characteristics3

Symbol

Expression

20 MHz4

30 MHz4

Unit

Min

Max

Min

Max

157

Random read or write cycle time

tRC

× T

250.0

—

166.7

—

158

RAS assertion to data valid (read)

tRAC

2.75

× T

C − 7.5

—

130.0

—

84.2

159

CAS assertion to data valid (read)

tCAC

1.25

× T

C − 7.5

—

55.0

—

34.2

160

Column address valid to data valid (read)

tAA

1.5

× T

C − 7.5

—

67.5

—

42.5

161

CAS deassertion to data not valid (read hold

time)

tOFF

0.0

—

0.0

—

162

RAS deassertion to RAS assertion

tRP

1.75

× T

C − 4.0

83.5

—

54.3

—

163

RAS assertion pulse width

tRAS

3.25

× T

C − 4.0

158.5

—

104.3

—

164

CAS assertion to RAS deassertion

tRSH

1.75

× T

C − 4.0

83.5

—

54.3

—

Chip Frequency

(MHz)

DRAM Type

(tRAC ns)

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

Notes This figure should be use for primary selection. For exact

and detailed timings see the following tables.

120

AA0475

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