DSP56852 datasheet(7/48 Pages) FREESCALE

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Introduction

56852 Technical Data, Rev. 8

Freescale Semiconductor

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56852 are organized into functional groups, as shown in Table 2-1 and

as illustrated in Figure 2-1. In Table 3-1, each table row describes the package pin and the signal or

signals present.

1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA

2. CLKOUT is muxed Address pin A20.

3. Four Address pins are multiplexed with the timer, CS3 and CLKOUT pins.

4. CS3 is multiplexed with external Address Bus pin A19.

5. Mode pins are multiplexed with External Data pins D13-D15 like A17and A18.

6. Four of these pins are multiplexed with SSI.

7. Two of these pins are multiplexed with 2 bits of the External Address Bus A17and A18.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of Pins

Power (VDD, VDDIO, or VDDA)

101

Ground (VSS, VSSIO,or VSSA)

101

Phase Lock Loop (PLL) and Clock

External Bus Signals

393

External Chip Select*

Interrupt and Program Control

Synchronous Serial Interface (SSI) Port*

Serial Communications Interface (SCI) Port*

Serial Peripheral Interface (SPI) Port

Quad Timer Module Port

JTAG/Enhanced On-Chip Emulation (EOnCE)

*Alternately, GPIO pins

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