56855 datasheet(21/52 Pages) FREESCALE

부품명	56855

상세설명	16-bit Digital Signal Controllers

PDF	52 Pages

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Supply Voltage Sequencing and Separation Cautions

56855 Technical Data, Rev. 6

Freescale Semiconductor

Figure 4-1 Maximum Run IDDTOTAL vs. Frequency (see Notes 1. and 5. in Table 4-4)

4.3 Supply Voltage Sequencing and Separation Cautions

Figure 4-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies.

Running core and performing external memory access. Clock at 120 MHz.

When VDD drops below VEI max value, an interrupt is generated.

Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active

for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is typically

100 mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.

120

150

100

120

EMI Mode5

MAC Mode1

56855 데이터시트(PDF) 21 Page - Freescale Semiconductor, Inc