DSP56853 datasheet(8/60 Pages) FREESCALE

8 / 60 page

56853 Technical Data, Rev. 6

Freescale Semiconductor

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56853 are organized into functional groups, as shown in Table 2-1 and

as illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signals

present.

1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA

2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed.

3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ.

Table 2-1 56853 Functional Group Pin Allocations

Functional Group

Number of Pins

Power (VDD, VDDIO, or VDDA)

(6, 11, 1)1

Ground (VSS, VSSIO,or VSSA)

(6, 10, 1)1

PLL and Clock

External Bus Signals

External Chip Select*

Interrupt and Program Control

Host Interface (HI)*

163

Enhanced Synchronous Serial Interface (ESSI0) Port*

Serial Communications Interface (SCI0) Ports*

Serial Communications Interface (SCI1) Ports*

Serial Peripheral Interface (SPI) Port*

Quad Timer Module Port*

JTAG/Enhanced On-Chip Emulation (EOnCE)

*Alternately, GPIO pins

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