RF226AP datasheet(13/46 Pages) NXP

13 / 46 page

Table 4. Recommended operating conditions (continued)

Characteristic

Symbol

Min

Typ

Max

Unit

Notes

Input external

clock input

common mode

voltage level

LVDS_122M8_P/N

Input

0.2

1.2

Input external

clock duty cycle

LVDS_122M8_P/N

Input

Rx BB external

output load (kick

-back filter)

ADC Input

Capacitance

Fixed capacitance

CINFIX

Switched capacitance

CINSW

0.6

ADC Input

Resistance

Resistor

Rcm2:Disconnected

kΩ

Resistor

Rcm3 :Disconnected

kΩ

ESD resistor RESD

Switch resistance

Rin_on

Switch resistance Ron

0.5

kΩ

TX BB input

common mode

0.5

TX BB input

signal level

Full scale from DAC

0.35

Frequency

Range

HB Lowest

4200

MHz

HB Highest

5000

MHz

MB lowest

3300

MHz

MB Highest

4200

MHz

LB Lowest

2500

MHz

LB Highest

3000

MHz

Notes:

1- LVDS_122M8_P and LVDS_122M8_N pins can be either inputs or outputs, but performance has not been validated when

used as an input.

3.1.3 Power Sequencing

Power rails can ramp simultaneously for all voltages, Core power supplies

VDD_DIG_CORE (0.9V ) should not begin to ramp before other supplies, and should

reach 90% of nominal voltage no more than 5ms after I/O rails ramp as shown in the

figure below. Analog 1.67 V supply and I/O 1.8 V supply are expected to begin ramp

simultaneously.

Electrical characteristics

RF112L0H Transceiver Data Sheet, Rev. A, 12/2020

NXP Semiconductors

Preliminary

Confidential Proprietary

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