AD9865BCPZ datasheet(43/48 Pages) AD

43 / 48 page

AD9865

Rev. A | Page 43 of 48

calibration and filter tuning routine is initiated upon RESET

returning high. To ensure sufficient power-on time of the

various functional blocks, RESET returning high should occur

no less than 10 ms upon power-up. If a digital reset signal from

a microprocessor reset circuit (such as ADM1818) is not

available, a simple R-C network referenced to DVDD can be

used to hold RESET low for approximately 10 ms upon power-

up.

ANALOG AND DIGITAL LOOP-BACK TEST MODES

The AD9865 features analog and digital loop-back capabilities

that can assist in system debug and final test. Analog loop-back

routes the digital output of the ADC back into the Tx data path

prior to the interpolation filters such that the Rx input signal

can be monitored at the output of the TxDAC or IAMP. As a

result, the analog loop-back feature can be used for a half- or

full-duplex interface, to allow testing of the functionality of the

entire IC (excluding the digital data interface).

For example, the user can configure the AD9865 with similar

settings as the target system, inject an input signal (sinusoidal

waveform) into the Rx input, and monitor the quality of the

reconstructed output from the TxDAC or IAMP to ensure a

minimum level of performance. In this test, the user can

exercise the RxPGA as well as validate the attenuation char-

acteristics of the RxLPF. Note that the RxPGA gain setting

should be selected such that the input does not result in clipping

of the ADC.

Digital loop-back can be used to test the full-duplex digital

interface of the AD9865. In this test, data appearing on the

Tx[5:0] port is routed back to the Rx[5:0] port, thereby

confirming proper bus operation. The Rx port can also be

three-stated for half- and full-duplex interfaces.

Table 26. SPI Registers for Test Modes

Address (Hex)

Bit

Description

0x0D

(7)

Analog loop-back

(6)

Digital loop-back

(5)

Rx port three-state

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