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PLV1812MDDFREP 데이터시트(PDF) 4 Page - Texas Instruments |
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PLV1812MDDFREP 데이터시트(HTML) 4 Page - Texas Instruments |
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4 / 33 page ![]() 4 Specifications 4.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage: VS = (V+) – (V–) –0.3 42 V Input pins (IN+, IN–) from (V– ) (2) –0.3 (V+) + 0.3 V Current into Input pins (IN+, IN–) –10 10 mA Output (OUT) voltage (Open-Drain) from (V–)(3) –0.3 42 V Output (OUT) voltage (Push-Pull) from (V–) –0.3 (V+) + 0.3 V Output (OUT) current (4) (5) (6) -10 10 mA Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Input terminals are diode-clamped to (V–). Input signals that can swing more than 0.3V beyond the supply rails must be current-limited to 10mA or less. (3) Output (OUT) for open drain can be greater than (V+) and inputs (IN+, IN–) as long as it is within the –0.3V to 42V range (4) The output is diode-clamped to (V-) for both output options, and diode clamped to (V+) for the push-pull output option. The open drain version does not have a clamp to V+. Please see the Outputs and ESD Protection section of the Application Information Section for more information. (5) Output sinking and sourcing current is internally limited to <35mA when operating within the Absolute Maximum output voltage limits. The Absoulute Maximum Output Current limit specified here is the maximum current through the clamp structure when exceeding the supply votlage below (V-) for both output options, or above (V+) for the push-pull option. (6) Short-circuit from output to (V–) or (V+). Continuous output short circuits at elevated supply voltages can result in excessive heating and exceeding the maximum allowed junction temperature, leading to eventual device destruction. 4.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. 4.3 Thermal Information - EP THERMAL METRIC(1) TLV1812-EP UNIT DDF (SOT-23) 8 PINS RθJA Junction-to-ambient thermal resistance 170.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 90.3 °C/W RθJB Junction-to-board thermal resistance 88.1 °C/W ψJT Junction-to-top characterization parameter 7.5 °C/W ψJB Junction-to-board characterization parameter 87.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance – °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report. TLV1812-EP, TLV1822-EP SNOSDJ3 – MAY 2024 www.ti.com 4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TLV1812-EP TLV1822-EP |
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