M68CBL05C datasheet(91/286 Pages) FREESCALE

91 / 286 page

Functional Description

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a

4096-CGMXCLK cycle delay.

1 = Stop mode recovery after 32 CGMXCLK cycles

0 = Stop mode recovery after 4096 CGMXCLKC cycles

NOTE

Exiting stop mode by pulling reset will result in the long stop recovery.

If using an external crystal oscillator, do not set the SSREC bit.

When the LVISTOP is enabled, the system stabilization time for power on

reset and long stop recovery (both 4096 CGMXCLK cycles) gives a delay

longer than the enable time for the LVI. There is no period where the MCU

is not protected from a low power condition. However, when using the short

stop recovery configuration option, the 32-CGMXCLK delay is less than the

LVI’s turn-on time and there exists a period in startup where the LVI is not

protecting the MCU.

STOP — STOP Instruction Enable Bit

STOP enables the STOP instruction.

1 = STOP instruction enabled

0 = STOP instruction treated as illegal opcode

COPD — COP Disable Bit

COPD disables the COP module. See Chapter 9 Computer Operating Properly (COP)

1 = COP module disabled

0 = COP module enabled

M68CBL05C 데이터시트(PDF) 91 Page - Freescale Semiconductor, Inc