Analog Integrated Circuit Device Data

Freescale Semiconductor

9

33291L

ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

ELECTRICAL PERFORMANCE CURVES

Figure 4. Valid Data Delay Time and

Valid Time Test Circuit

Figure 5. Enable and Disable Time Test Circuit

Figure 6. Valid Data Delay Time and

Valid Time Waveforms

Figure 7. Enable and Disable Time Waveforms

SCLK

SO

33291L

Under

Test

CS

SO

33291L

Under

Test

SCLK

SO

SO

(Low-to-High)

(High-to-Low)

0.2 VDD

0.7 VDD

0.7 VDD

0.2 VDD

0.7 VDD

50%

0.2 VDD

0

< 50 ns

< 50 ns

5.0 V

SO (Low-to-High) is for an output with internal conditions such that

the low-to-high transition of CS causes the SO output to switch from

high to low.

90%

10%

10%

10%

90%

90%

CS

SO

SO

(High-to-Low)

(Low-to-High)

0.2 VDD

0.7 VDD

< 50 ns

< 50 ns

tSO(EN)

tSO(DIS)

tSO(EN)

tSO(DIS)

VTri-State

5.0 V

0

tSO(dis

VTri-State

VOH

1. SO (high-to-low) waveform is for SO output with internal conditions such

that SO output is low except when an output is disabled as a result of de-

tecting a circuit fault with CS in a High Logic state; e.g., open load.

2. SO (low-to-high) waveform is for SO output with internal conditions such

that SO output is high except when an output is disabled as a result of de-

tecting a circuit fault with CS in a High Logic state; e.g., shortened load.