| 전자부품 데이터시트 검색엔진 |
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TMP112A/B/N 데이터시트(PDF) 31 Page - Texas Instruments |
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TMP112A/B/N 데이터시트(HTML) 31 Page - Texas Instruments |
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31 / 47 page ![]() For TMP112Dx device, where the 5th pin is ADD0, the pin can easily be connected to one of the 4 edge pins for setting the device address as shown in Figure 8-5. For devices where the 5th pin is ALERT, a 4 mil trace can be routed between pins 1 and 5 or pins 2 and 4 as shown in Figure 8-6. 5 2 4 1 3 0.1 µF RPULLUP Via to Power Plane Via to Ground Plane RPULLUP Not to scale Figure 8-5. ADD0 Pin Layout Example 5 2 4 1 3 RPULLUP Via to Power Plane Via to Ground Plane RPULLUP 0.1 µF R1PULLUP Not to scale Figure 8-6. ALERT Pin Layout Example www.ti.com TMP112 SBOS473J – MARCH 2009 – REVISED FEBRUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TMP112 |
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