Analog Integrated Circuit Device Data

Freescale Semiconductor

13

33991

TIMING DESCRIPTIONS AND DIAGRAMS

COMMUNICATION MEMORY MAPS

TIMING DESCRIPTIONS AND DIAGRAMS

Figure 5. Single 16-Bit Word SPI Communication

Figure 6. Multiple 16-Bit Word SPI Communication

DATA INPUT

The input Shift register captures data at the falling edge of

the SCLK clock. The SCLK clock pulses exactly 16 times only

inside the transmission windows (CS in a logic [0] state). By

the time the CS signal goes to logic [1] again, the contents of

the Input Shift register are transferred to the appropriate

internal register, according to the address contained in bits

15-13. The minimum time CS should be kept high depends

on the internal clock speed. That data is specified in the SPI

Interface Timing Table. It must be long enough so the internal

clock is able to capture the data from the input Shift register

and transfer it to the internal registers.

DATA OUTPUT

At the first rising edge of the SCLK clock, with the CS at

logic [0], the contents of the Status Word register are

transferred to the Output Shift register. The first 16 bits

clocked out are the status bits. If data continues to clock in

before the CS transitions to a logic [1], the device to shift out

the data previously clocked in FIFO after the CS first

transitioned to logic [0].

COMMUNICATION MEMORY MAPS

The 33991device is capable of interfacing directly with a

micro controller, via the 16-bit SPI protocol described and

specified below. The device is controlled by the

microprocessor and reports back status information via the

SPI. This section provides a detailed description of all

registers accessible via serial interface. The various registers

control the behavior of this device.

A message is transmitted by the master beginning with the

MSB (D15) and ending with the LSB (D0). Multiple

messages can be transmitted in succession to accommodate

those applications where daisy chaining is desirable, or to

confirm transmitted data, as long as the messages are all

multiples of 16 bits. Data is transferred through daisy chained

devices, illustrated in Figure 5. If an attempt is made to latch

in a message smaller than 16 bits wide, it is ignored.

The 33991 uses six registers to configure the device and

control the state of the four H-bridge outputs. The registers

are addressed via D15-D13 of the incoming SPI word, in

Table 2.

In te r n a l re g is t e r s a re

lo a d e d s o m e tim e

a fte r th is e d g e

CS B

SI

SC L K

D1 5

D1

D2

D3

D4

D5

D6

D7

D8

D9

D1 4

D1 3

D1 2

D1 1

D1 0

OD 1 2

D0

OD 1 3

OD 1 4

OD 1 5

OD 6

OD 7

OD 8

OD 9

OD 1 0

OD 1 1

OD 1

OD 2

OD 3

OD 4

OD 5

1 .

S O is t r i-s t at e d w h en C S B is lo gic 1.

NO T E S :

OD 0

SO

O u t p ut s h if t regis t e r is

lo ad ed he r e

CS

SCLK

SI

SO

CS is logic 1.

CS B

SI

SC L K

D1 5

D1 *

D2 *

D1 3 *

D1 4 *

D1 5 *

D0

D1

D1 4

D1 3

D2

D0 *

OD 1 3

OD 1 4

OD 1 5

D1 4

D1 5

OD 0

OD 1

OD 2

D1

D2

D1 3

1.

S O is t ri- s t at ed w h e n C S B is lo gic 1 .

2 .

D 1 5 , D 1 4 , D 1 3 , .. ., a n d D 0 re fe r to th e fir s t 1 6 b its o f d a ta in to th e G D IC .

3 .

D 1 5 * , D 1 4 * , D 1 3 * , ... , a n d D 0 * re fe r to th e m o s t re c e n t e n try o f p ro g r a m d a ta in to th e G D IC .

4 .

O D 1 5 , O D 1 4 , O D 1 3 , ..., a n d O D 0 r e fe r to th e firs t 1 6 b its o f fa u lt a n d s t a t u s d a ta o u t o f th e G D IC .

NO T E S :

D0

SO

CS

SI

SO

SCLK

CS is logic 1.

33991.

33991.

33991.