MPC866P datasheet(48/96 Pages) FREESCALE

48 / 96 page

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor

CPM Electrical Characteristics

Figure 40. Boundary Scan (JTAG) Timing Diagram

12 CPM Electrical Characteristics

This section provides the AC and DC electrical specifications for the communications processor module (CPM) of

the MPC866/859.

12.1 PIP/PIO AC Electrical Specifications

Table 16 shows the PIP/PIO AC timings as shown in Figure 41 through Figure 45.

Table 16. PIP/PIO Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

Data-in setup time to STBI low

—

Data-In hold time to STBI high

2.5 – t3 1

t3 = Specification 23

—clk

STBI pulse width

1.5

—

clk

STBO pulse width

1 clk – 5ns

—

Data-out setup time to STBO low

—

clk

Data-out hold time from STBO high

—

clk

STBI low to STBO low (Rx interlock)

—

clk

STBI low to STBO high (Tx interlock)

—

clk

Data-in setup time to clock high

—

Data-in hold time from clock high

7.5

—

Clock low to data-out valid (CPU writes data, control, or direction)

—

TCK

Output

Signals

Output

Signals

Output

Signals

J92

J94

J93

J95

J96

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