MPC5200B datasheet(21/78 Pages) FREESCALE

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Electrical and Thermal Characteristics

MPC5200B Data Sheet, Rev. 1

Freescale Semiconductor

Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing

3.3.5.3

Memory Interface Timing-DDR SDRAM Read Command

The SDRAM Memory Controller uses a 1/4 period delayed MDQS strobe to capture the MDQ data. The

1/4 period delay value is calculated automatically by hardware.

Table 19. Standard SDRAM Write Timing

Sym

Description

Min

Max

Units

SpecID

tmem_clk

MEM_CLK period

7.5

—

A5.8

tvalid

Control Signals, Address and MBA Valid

after rising edge of MEM_CLK

—tmem_clk*0.5+0.4

A5.9

thold

Control Signals, Address and MBA Hold after

rising edge of MEM_CLK

tmem_clk*0.5

—

A5.10

DMvalid

DQM valid after rising edge of MEM_CLK

—

tmem_clk*0.25+0.4

A5.11

DMhold

DQM hold after rising edge of Mem_clk

tmem_clk*0.25-0.7

—

A5.12

datavalid

MDQ valid after rising edge of MEM_CLK

—

tmem_clk*0.75+0.4

A5.13

datahold

MDQ hold after rising edge of MEM_CLK

tmem_clk*0.75-0.7

—

A5.14

MEM_CLK

Control Signals

MDQ (Data)

MA (Address)

NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Active

NOP

WRITE

NOP

thold

Row

Column

MBA (Bank Selects)

datahold

datavalid

tvalid

thold

tvalid

thold

tvalid

DQM (Data Mask)

DMvalid

DMhold

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