MPC866PCZP100A datasheet(39/96 Pages) FREESCALE

39 / 96 page

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor

Bus Signal Timing

P50

CLKOUT to PCOE, IORD, PCWE,

IOWR assert time (MAX = 0.00 x

B1 + 11.00)

—

11.00

—

11.00

—

11.00

—

11.00

P51

CLKOUT to PCOE, IORD, PCWE,

IOWR negate time (MAX = 0.00 x

B1 + 11.00)

2.00

11.00

2.00

11.00

2.00

11.00

2.00

11.00

P52

CLKOUT to ALE assert time (MAX

= 0.25 x B1 + 6.30)

7.60

13.80

6.30

12.50

5.00

11.30

3.80

10.00

P53

CLKOUT to ALE negate time (MAX

= 0.25 x B1 + 8.00)

—

15.60

—

14.30

—

13.00

—

11.80

P54

PCWE, IOWR negated to D(0:31)

invalid1 (MIN = 0.25 x B1 – 2.00)

5.60

—

4.30

—

3.00

—

1.80

—

P55

WAITA and WAITB valid to

CLKOUT rising edge1 (MIN = 0.00

x B1 + 8.00)

8.00

—

8.00

—

8.00

—

8.00

—

P56

CLKOUT rising edge to WAITA and

WAITB invalid1 (MIN = 0.00 x B1 +

2.00)

2.00

—

2.00

—

2.00

—

2.00

—

PSST = 1. Otherwise, add PSST times cycle time.

PSHT = 0. Otherwise, add PSHT times cycle time.

These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA

current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See

PCMCIA Interface in the

MPC866 PowerQUICC User’s Manual.

Table 11. PCMCIA Timing (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

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