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MPC18730EPR2 데이터시트(PDF) 25 Page - Freescale Semiconductor, Inc

부품명 MPC18730EPR2
상세설명  Power Management IC with Five Regulated Outputs Programmed Through 3 Wire Serial Interface
PDF  35 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC18730EPR2 데이터시트(HTML) 25 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
25
18730
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Ext / Int: Clock Select control 1
1 = External Clock
0 = Internal Clock
2FS: Clock Select control 2
1 = 2FS on
0 = 2FS off
RSTB Sleep: RSTB Sleep Monitor
*1
1 = RSTB SLEEP Monitor off
0 = RSTB SLEEP Monitor on
S_Off_VG: VG Top side transistor off
1 = Synchronous Rectification Off
0 = Synchronous Rectification On
VG_Duty[3]: VG Duty Control MSB
1 = VG Duty[3] is high
0 = VG Duty[3] is low
VG_Duty[2]: VG Duty Control Bit 2
1 = VG Duty[2] is high
0 = VG Duty[2] is low
VG_Duty[1]: VG Duty Control Bit1
1 = VG Duty[1] is high
0 = VG Duty[1] is low
VG_Duty[0]: VG Duty Control LSB
1 = VG Duty[0] is high
0 = VG Duty[0] is low
VG is controlled by PFM method. This register can change
the duty by 16 steps.
Refer to Table 15, VGATE Duty Settings on page 23 for
the correspondence between the VG Duty maximum values
and register settings.
VO1_SENSE[6]: Reference DAC MSB
1 = VO1_SENSE[6] on
0 = VO1_SENSE[6] off
VO1_SENSE[5]: Reference DAC Bit5
1 = VO1_SENSE5] on
0 = VO1_SENSE[5] off
VO1_SENSE[4]: Reference DAC Bit4
1 = VO1_SENSE[4] on
0 = VO1_SENSE[4] off
VO1_SENSE[3]: Reference DAC Bit3
1 = VO1_SENSE[3] on
0 = VO1_SENSE[3] off
VO1_SENSE[2]: Reference DAC Bit2
1 = VO1_SENSE[2] on
0 = VO1_SENSE[2] off
VO1_SENSE[1]: Reference DAC Bit1
1 = VO1_SENSE[1] on
0 = VO1_SENSE[1] off
VO1_SENSE[0] on
0 = VO1_SENSE[0] off
S_Off_VO1_SENSE: DDC1 Top side (Ni_mh) / Bottom
side (Li_ion) transistor off
1 = Synchronous Rectification Off
0 = Synchronous Rectification On
Refer to Table 10, Output Voltage of VO1_SENSE on
page 19 for the correspondence between the output voltage
and register settings.
Table 19. Clock Select Register
0010
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
Ext/Int
Half Freq
RSTB sleep
S_Off_VG
VG_Duty [3]
VG_Duty[2]
VG_Duty[1]
VG_Duty[0]
Default
0
0
1
0
0
0
0
0
Table 20. VO1_SENSE Output Voltage Register
0011
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
VO1_SENSE
[6]
VO1_SENSE
[5]
VO1_SENSE
[4]
VO1_SENSE
[3]
VO1_SENSE
[2]
VO1_SENSE
[1]
VO1_SENSE
[0]
S_Off_VO1_SENSE
Default
1
0
0
0
0
0
0
0



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