XRT83SL216

15

REV. 1.0.0

16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

1.0

RECEIVE PATH LINE INTERFACE

The receive path consists of 16 independent E1 receivers. The following section describes the complete

receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified block diagram of the receive

path is shown in Figure 3.

1.1

Peak Detector/Data Slicer

In the receive path, the line signal is coupled into the RTIP and RRing pins via a 2:1 transformer and are

converted into digital pulses by an equalizer and an adaptive data slicer. Clock and data signals are recovered

from the output of the slicer with the help of a digital PLL that provides excellent jitter accommodation for high

input jitter tolerance.

1.2

Clock and Data Recovery

The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the

incoming data stream and outputs a clock that’s in phase with the incoming signal. In the absence of an

incoming signal, RCLK maintains its timing by using MCLK as its reference. The recovered data can be

updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To update data on

the falling edge of RCLK, set RCLKinv to "1" in the appropriate global register. Figure 4 is a timing diagram of

the receive data updated on the rising edge of RCLK. Figure 5 is a timing diagram of the receive data updated

on the falling edge of RCLK. The timing specifications are shown in Table 1.

HDB3

Decoder

Rx Jitter

Attenuator

Clock & Data

Recovery

Rx Equalizer &

Peak Detector

RTIP

RRING

RCLK

RPOS

RNEG

RCL K

RP O S

or

RNE G

R

DY

RCL K

R

RCL K

F

R

OH

RCLK

RPOS

or

RNEG

R

DY

RCLK

F

RCLK

R

R

OH