XRK7933

PRELIMINARY

xr

INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

REV. P1.0.1

7

APPLICATIONS INFORMATION

The XRK7933 is a dual clock PLL with on–chip Intelligent Dynamic Clock Switch circuitry.

primary clock: The input CLK selected by Sel_Clk.

secondary clock: The input CLK NOT selected by Sel_Clk.

PLL reference signal: The CLK selected as the PLL reference signal by Sel_Clk or the Intelligent Dynamic

Clock Switch. The Intelligent Dynamic Clock Switch can override Sel_Clk.

Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as the PLL reference signal. Clk_Selected (H)

indicates CLK1 is selected as the PLL reference signal.

Inp0bad, Inp1bad: Inp0bad is latched (H) when CLK0 is stuck (H) or (L) for at least one Ext_FB period, or if one

of the inputs CLK0 or CLK0 is floating. Inp1bad is latched (H) when CLK1 is stuck (H) or (L) for at least one

Ext_FB period, or if one of the inputs CLK1 or CLK1 is floating. Both Inp0bad and Inp1bad are latched (H)

when Ext_FB is stuck (H) or (L) for at least one Qa period, or if one of the inputs Ext_FB or Ext _FB is floating.

Both Inp0bad and Inp1bad are cleared (L) on assertion of Alarm_Reset. The status functions Inp0bad and

Inp1bad are active for Man_Override (H) or (L).

Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock.

Alarm_Reset: Asserted by a negative edge. Generates a one–shot reset pulse that clears INPUT_BAD latches

and Clk_Selected latch.

PLL_En: While (L), the PLL reference signal is substituted for the VCO output.

MR: While (L), internal dividers are held in reset which holds all Q outputs LOW.

(IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be

the CLK selected by Sel_Clk. If Ext_FB misses at least one pulse, Qa and Qb outputs will drop to a minimum

frequency (~20MHz) for 1-uS, or until Ext_FB shows any activity, whichever is longer. This prevents the Qa

and Qb frequencies from rising due the PLL incorrectly interpreting an intermittent Ext_FB as a VCO running

too slow.

Intelligent Dynamic Clock Switch is enabled. The first CLK to fail will latch it’s INP_BAD (H) status flag and

select the other input as the Clk_Selected for the PLL reference clock. Once latched, the Clk_Selected and

INP_BAD remain latched until assertion of Alarm_Reset which clears all latches (INP_BADs are cleared and

Clk_Selected = Sel_Clk).

If both Inp0bad and Inp1bad are (H), either due to both CLK0 and CLK1 having missed at least 1 pulse each or

Ext_FB having missed at least 1 pulse, then Qa and Qb outputs will drop to a minimum frequency (~20MHz)

until such time as Alarm_Reset_b is asserted.

and Clk_Selected will be latched (L) indicating CLK0 is the PLL reference signal. While neither INP_BAD is latched

(H), the Clk_Selected can be freely changed with Sel_Clk. Whenever a CLK switch occurs, (manually or by the

Intelligent Dynamic Clock Switch), following the next negative edge of the newly selected PLL reference signal, the

next positive edge pair of Ext_FB and the newly selected PLL reference signal will slew to alignment.

To calculate the overall uncertainty between the input CLKs and the outputs from multiple XRK7933’s, the

following procedure should be used. Assuming that the input CLKs to all XRK7933’s are exactly in phase, the

total uncertainty will be the sum of the static phase offset, max I/O jitter, and output to output skew.

During a dynamic switch, the output phase between two devices may be increased for a short period of time. If

the two input CLKs are 400ps out of phase, a dynamic switch of an XRK7933 will result in an instantaneous

phase change of 400ps to the PLL reference signal without a corresponding change in the output phase (due

to the limited response of the PLL). As a result, the I/O phase of a device, undergoing this switch, will initially