5

Date: 6/23/04

SP3483 Low Power Slew Rate Limited Half-Duplex RS485 Transceivers

© Copyright 2004 Sipex Corporation

Figure 2. Driver Propagation Delay Test Circuit

Figure 4. Driver Enable and Disable Timing Circuit,

Output HIGH

Figure 1. Driver DC Test Load Circuit

Figure 6. Receiver Propagation Delay Test Circuit

Figure 7. Receiver Enable and Disable Timing Circuit

R

R

D

GENERATOR

(NOTE 1)

50Ω

S1

OUT

(NOTE 2)

1.5V

2

D

GENERATOR

(NOTE 1)

50Ω

S1

OUT

(NOTE 2)

1.5V

2

D

GENERATOR

(NOTE 1)

50Ω

S1

OUT

(NOTE 2)

D

0V OR 3V

GENERATOR

(NOTE 1)

50Ω

1.5V

0V

R

OUT

(NOTE 2)

2

1.5V

-1.5V

S3

GENERATOR

(NOTE 1)

50Ω

(NOTE 2)

R

1k

S1

S2

Figure 5. Driver Enable and Disable Timing Circuit,

Output LOW

GENERATOR

(NOTE 1)

50Ω

OUT

D

60Ω

Figure 3. Driver Differential Output Delay and Transition

Time Circuit