1999 Nov 12

13

Philips Semiconductors

Preliminary specification

NTSC Picture-In-Picture (PIP) controller

SAB9082

Acquisition channel ADCs and clamping

The analog input signals are converted to digital signals by

three ADCs per channel. The resolution of the ADCs is

8 bits (DNL is 7 bits and INL is 6 bits) and the sampling is

performed at the system clock frequency of 28 MHz for the

components on internal references.

The inputs should be AC coupled and an internal clamp

circuit (using external clamp capacitors) will clamp the

luminance channels and, for the chrominance channels, to

starts at the active edge of the burst key. Internal video

buffers amplify the standard Y, U and V input signals to

the correct ADC levels.

PLL

The PLL generates an internal system clock of

1792

× f

28 MHz.

DACs and video buffers

The 28 MHz digital video signals are fed to the 8-bit DACs

that produce the required analog video signals. The video

buffers amplify these signals prior to being fed to the

output to drive another device.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611, Part E”, dated 14 December 1992.

ESD LEVELS

The standard ESD specification is JEDEC Class II (2 kV Human Body Model, 200 V Machine Model) unless indicated

otherwise.

Table 5

ESD performance

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage range

−0.5

5.0

V

storage temperature

−25

+150

°C

ambient temperature

0

70

°C

electrostatic discharge handling

−

2kV

thermal resistance

−

45

K/W

maximum power dissipation

−

1.0

W

PIN

SYMBOL

HUMAN BODY MODEL (V)

MACHINE MODEL (V)

68

FBL

1000

standard specification

69

PKOFF

1000

70

DVSYNC

1000

72

SVSYNC

1000

73

SCL

1000

74

SDA

1000

rest in range 1 to 17

all other pins

standard specification

rest in range 64 to 100