24CSM01 datasheet(19/63 Pages) MICROCHIP

19 / 63 page

 2023 Microchip Technology Inc. and its subsidiaries

Preliminary

DS20006781B

-page 19

24CSM01

7.0

READ OPERATIONS

Read operations are initiated the same way as write

operations with the exception that the Read/Write

Select (R/W) bit in the device address byte must be a

logic ‘1’. There are three read operations:

• Current Address Read

• Random Read

• Sequential Read

7.1

Current Address Read

The 24CSM01 contains an internal Address Pointer

that maintains the word address of the last byte

accessed, internally incremented by one. Therefore, if

the previous read access was to address ‘n’ (n is any

legal address), the next current address read operation

would access data from address ‘n+1’.

A current address read operation will output data

according to the location of the internal Address

Pointer. This is initiated with a Start condition followed

by a valid device address byte with the R/W bit set to

logic ‘1’. The device will ACK this sequence and the

current address data byte is serially clocked out on the

SDA line. All types of read operations will be terminated

if the host does not respond with an ACK (it NACKs)

during the ninth clock cycle, which will force the device

into Standby mode. After the NACK response, the host

may send a Stop condition to complete the protocol, or

it can send a Start condition to begin the next

sequence.

FIGURE 7-1:

CURRENT ADDRESS READ

SCL

SDA

MSb

D7 D6

D2 D1 D0

MSb

Data Byte (n)

Device Address Byte

NACK

from

Host

Stop

Host

ACK

from

Client

Start

Host

Note 1: “Don’t care” bit.

(1)

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