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LAN8804/ZMXC1 데이터시트(PDF) 20 Page - Microchip Technology

부품명 LAN8804/ZMXC1
상세설명  4-Port Gigabit Ethernet Transceiver with QSGMII Support
PDF  91 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN8804/ZMXC1 데이터시트(HTML) 20 Page - Microchip Technology

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LAN8804
DS00003591G-page 20
© 2024 Microchip Technology Inc. and its subsidiaries
Device Mode
Configuration
Straps
MODE_SEL[4:0]
VIS
Configures the specific functional mode of all PHYs. The
MODE[4:0] configuration straps are sampled and latched at
power-up/reset and are defined in Section 3.3.1, "Device Mode
Select (MODE_SEL[4:0])".
PHY Broadcast
Mode
Configuration
Strap
ALLPHYAD
VIS
Configures the default support for PHY Broadcast access
using PHY Address 0. The
ALLPHYAD configuration strap is
sampled and latched at power-up/reset and are defined as fol-
lows:
0: Enable PHY Broadcast accesses by default
1: Disable PHY Broadcast accesses by default
Refer to Section 3.3.3, "All PHYs Address (ALLPHYAD)" for
additional information.
LED Mode
Configuration
Strap
LED_MODE
VIS
Configures the device’s LED behavior as Individual or Tri-
Color. All 8 LEDs are configured with identical behavior. The
LED_MODE configuration strap is sampled and latched at
power-up/reset and is defined as follows:
0: Tri-color-LED mode
1: Individual-LED mode
Refer to Section 3.3.4, "LED Mode Select (LED_MODE)" for
additional information.
TABLE 3-8:
POWER AND GROUND PINS
Name
Symbol
Buffer
Type
Description
+2.5/3.3V
Analog I/O Power
Supply
VDDAH
VDDAH_P[3:0]
VDDAH_SERDES
VDDAH_PLL_PTP
VDDAH_ABPVT
P
+2.5/3.3V analog I/O power supply
+2.5/3.3V
Analog Power
Supply
VDD33REF
P
+2.5/3.3V analog power supply
+1.1V Analog
Power Supply
VDDAL_ADC_A_P[3:0]
VDDAL_ADC_B_P[3:0]
VDDAL_ADC_C_P[3:0]
VDDAL_ADC_D_P[3:0]
VDDAL_PLL
VDDAL_SERDES
VDDTXL_SERDES
VDDAL_CK125
P
+1.1V analog power supply
+3.3/2.5/1.8V
Variable I/O
Power Supply
Input
VDDIO
VDDIO_1
P
+3.3/2.5/1.8V variable I/O digital power supply input
+1.1V Digital
Core Power
Supply Input
VDDCORE
P
+1.1V digital core power supply input
TABLE 3-7:
CONFIGURATION STRAP INPUT PINS (CONTINUED)
Name
Symbol
Buffer
Type
Description



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