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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SC68C198 데이터시트(PDF) 39 Page - NXP Semiconductors |
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SC68C198 데이터시트(HTML) 39 Page - NXP Semiconductors |
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39 / 49 page  Philips Semiconductors Product specification SC26C198 SC68C198 SC26L198 SC68L198 Octal UART with TTL compatibility at 3.3V and 5V supply voltages 1995 May 1 374 AC ELECTRICAL CHARACTERISTICS5 (26C198 and 68C198) SYMBOL FIGURE PARAMETER LIMITS UNIT SYMBOL FIGURE PARAMETER MIN TYP MAX UNIT RESET TIMING tRES RESET pulse width 10 Sclk BUS TIMING tAS A0-A7 setup time before Sclk C3 rising edge 10 3 ns tAH A0-A7 hold time after Sclk C3 rising edge 18 12 ns tCS CEN setup time before Sclk C1 high (ASYNC) 5 ns tCS CEN setup time before Sclk C2 high (SYNC) 5 ns tCH CEN hold time after Sclk C3 high (SYNC) 15 1.5 Sclk ns tCH CEN hold time after Sclk C4 high (ASYNC)1 25 1.5 Sclk ns tSTP CEN high after C4 end. To terminate cycle (SYNC) 18 Sclk tRWS W-Rn setup time before Sclk C2 rising edge 5 ns tRWH W-Rn hold time after Sclk C3 rising edge 20 1.5 Sclk ns tDD Read cycle Data valid after Sclk C3 falling edge 25 37 ns tDF Read cycle data bus floating after CEN high (ASYNC) 20 35 ns tDF Read cycle data bus floating after C4 end (SYNC) 20 35 ns tDS Write cycle data setup time before Sclk C4 rising edge 25 15 ns tDH Write cycle data hold time after Sclk C4 rising edge 30 18 ns tRWD High time between CEN low (ASYNC) 12 10 ns I/O PORT PIN TIMING tPS I/O input setup time before Sclk C3 falling edge (Read IPR) 20 ns tPH I/O input hold time after Sclk C4 rising edge (Read IPR) 18 ns tPD I/O output valid from: Write Sclk C4 rising edge (write to I/OPIOR) 50 ns INTERRUPT TIMING tIR IRQN from: Internal interrupt source active bid Software reset to IRQN inactive Write IMR (clear IMR bit after C4 end) 22 3 43 50 Sclk Sclk ns tDD Interrupt vector valid after C3 falling edge, IACKN cycle 25 37 ns Tx / Rx CLOCK TIMING, External2 tRX RxC high or low time 20 ns fRX RxC frequency (16 X) (1 X) 0 0 16 1 MHz tTX TxC high or low time 20 ns fTX TxC frequency (16 X) (1 X) 0 0 16 1 MHz tRF Tx / Rx clock rise and fall times 20 ns TRANSMITTER TIMING tTXD TxD output delay from TxC low 100 ns tTCS TxC output delay from TxD output data -20 20 ns RECEIVER TIMING tRXS RxD data setup time to RxC high (data) 30 ns RXH RxD data hold time from RxC high (data) 30 ns TsSTRT RxD data setup time to RxC high (Start Bit) 17 / 32 16X clk Sclk TIMING3 Tsclkl Min low time at Vil (0.8V) 11 ns Tsclkh Min high time at Vih (2.0V) 11 ns Fsclk Sclk frequency 33 MHz T/RFsclk Sclk rise/fall time (0.8 to 2.0Volts) 3 / 3 ns |
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