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TMP112BIDRLR 데이터시트(PDF) 30 Page - Texas Instruments |
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TMP112BIDRLR 데이터시트(HTML) 30 Page - Texas Instruments |
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30 / 41 page ![]() 8.3.2 Layout Example Serial Bus Traces Pull-Up Resistors Supply Bypass Capacitor Via to Power or Ground Plane Via to Internal Layer Supply Voltage SCL GND ALERT ADD0 V+ SDA Ground Plane for Thermal Coupling to Heat Source Heat Source Figure 8-5. Layout Example (SOT563-6 package) There are special considerations that need to be taken for the TMP112 X2SON package. These considerations are due to the center pad being electrically connected to either address or alert (depending on the orderables shown in Address and Alert Variant Device Target Address) and because of the dimensions of the package and the pads. With the address option, the center pad can be directly connected with a trace on the same layer to one of the 4 edge pins for setting the device address as shown in Figure 8-6. TMP112, TMP112D SBOS473L – MARCH 2009 – REVISED JULY 2024 www.ti.com 30 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TMP112 TMP112D |
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