Philips Semiconductors

Product specification

SC28C94

Quad universal asynchronous receiver/transmitter (QUART)

1998 Aug 19

29

RESET

SD00169

Figure 11. Reset Timing

RDN

CEN

I/O as Output

I/O as Input

WRN

OLD DATA

NEW DATA

I/O PINS MUST BE STABLE FOR NON-CHANGING BUS DATA DURING THE READ.

NOTE: I/O PIN DATA IS NOT LATCHED

SD00170

Figure 12. I/O Port Timing

WRN

INTERRUPT1

OUTPUT

RDN

INTERRUPT1

OUTPUT

VM

tIR

tIR

VOL +0.5V

VOL +0.5V

VOL

VOL

NOTES:

1. INCLUDES I/O WHEN USED AS TxRDY or RxDY/FFULL OUTPUTS AS WELL AS IRQN.

2. THE TEST FOR OPEN DRAIN OUTPUTS IS INTENDED TO GUARANTEE SWITCHING OF THE OUTPUT TRANSISTOR. MEASUREMENT OF THIS RESPONSE IS

REFERENCED FROM THE MIDPOINT OF THE SWITCHING SIGNAL, VM, TO A POINT 0.5V ABOVE VOL. THIS POINT REPRESENTS NOISE MARGIN THAT AS-

SURES TRUE SWITCHING HAS OCCURRED. BEYOND THIS LEVEL, THE EFFECTS OF EXTERNAL CIRCUITRY AND TEST ENVIRONMENT ARE PRONOUNCED

AND CAN GREATLY AFFECT THE RESULTANT MEASUREMENT.

SD00171

Figure 13. Interrupt Timing