SC4000 datasheet(13/52 Pages) PHILIPS

13 / 52 page

2000 Sep 07

Philips Semiconductors

Preliminary speciﬁcation

Universal Timeslot Interchange

SC4000

Writing to the routing memory is syn-

chronized with SCbus timing. So rout-

ing information can be changed only on

time slot boundaries. All input data is

buffered in holding registers. The entire

holding register is transferred to the out-

put registers on a frame boundary basis.

All frame-bounded time slots incur a

one frame delay as they pass through the

switch. Switching data in this fashion

supports time slot bundling.

The SO outputs are tri-state controlled

on time slot boundaries by the Source

Routing Memory Switch Output Enable

Bit. This allows SO outputs from multi-

ple devices to be connected to a com-

mon line. The data sample position of

both the SCbus and the Local bus can be

selected for either 50% or 75% of the bit

cell.

In addition to switching local bus serial

data to and from the SCbus, the SC4000

provides a means of switching parallel

data through the microprocessor inter-

face to the SCbus. A frame boundary in-

terrupt helps control the timing of

parallel data accesses. Direct reading and

writing of parallel access register con-

tents makes for an efficient data transfer.

When using direct access, the control-

ling processor places the address of the

target channel on the address bus. In

this way, data can be read or written in a

single cycle. To avoid data corruption,

the application should not access the

channel for a time period defined as four

clocks before and four clocks after the

frame boundary.

The Source Routing Memory Local

Connect Enable mode allows the switch-

ing of any destination channel to

any source channel without SCbus

intervention. This mode accommodates

either serial or parallel data transfer.

Since data passes through the switch

twice in this mode, there is a two-frame

delay from input to output.

Diagnostic mode electrically disconnects

the SC4000 from the SCbus but allows

access through the local bus. This mode

is particularly useful for running board

diagnostics without upsetting the

SCbus. A Master Clock source is

required to run this mode.

The SC4000 pinout anticipates a future

version of the chip that includes an in-

ternal HDLC controller for the message

channel. To remain compatible with this

and other subsequent versions of the

SC4000, applications must write 0 to

all “Reserved (read only)” configuration

registers.

Figure 1. Destination and Source Switch Function Block

SI_[3:0]

D_[7:0]

SO_[3:0]

OUTPUT

ENABLE

INTERNAL PARALLEL

READ

SOURCE

DESTINATION

PARALLEL

ACCESS

INPUT

HOLDING

PARALLEL

OUTPUT

HOLDING REGISTER

TIMESLOT & PORT

OUTPUT ENABLE

OUTPUT

HOLDING

INPUT

HOLDING

TIMESLOT,

PORT AND LOCAL

CONNECT ENABLE

1 OF 128 SOURCE SWITCH

1 OF 128 DESTINATION SWITCH

ROUTING MEMORY

SD_[15:0]

ACCESS

ENABLE

W/R_N

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