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HMC1061LC5TR-R5 데이터시트(PDF) 8 Page - Analog Devices

부품명 HMC1061LC5TR-R5
상세설명  DC to 18 GHz, Ultra Wideband, Dual Rank, 4 GSPS Track-and-Hold Amplifier
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HMC1061LC5TR-R5 데이터시트(HTML) 8 Page - Analog Devices

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HMC1061LC5
Data Sheet
Rev. B | Page 8 of 18
Pin No.
Mnemonic
Description
25, 29
VCCOF2,
VCCOF1
Positive VCC Supplies for the Front End of the Output Buffer Circuitry. VCCOF2 is for the output of the IC, while VCCOF1
is for the interstage buffer between the first and second rank track-and-hold amplifiers. Nominal voltage = 2 V
(VCCOF1 + VCCOF2), current = 47 mA (nominal). See Figure 11 for the interface schematic.
27, 31
VCCTH2,
VCCTH1
Positive Power Supplies for the Track-and-Hold Amplifier Portions of the HMC1061LC5. VCCTH2 is the supply
for second rank track-and-hold core circuitry and VCCTH1 is the supply for the first rank track-and-hold core
circuitry. Nominal voltage = 2 V (VCCTH1 + VCCTH2), current = 140 mA (nominal). See Figure 12 for the interface
schematic.
EPAD
Exposed Pad. The exposed pad must be connected to VEE.
INTERFACE SCHEMATICS
GNDA
Figure 3. GNDA Interface Schematic
INP,
INN
50Ω
Figure 4. INP and INN Interface Schematic
T/H
CLOCK
BUFFER
CLKP
VEECLK1, VEECLK2
VEE
CLKN
VCCCLK1, VCCCLK2
Figure 5. VEECLKx and VCCCLKx Interface Schematic
GNDC
Figure 6. GNDC Interface Schematic
CLKAN, CLKAP,
CLKBN, CLKBP
50Ω
Figure 7. CLKxN and CLKxP Interface Schematic
CLK_SELECT
VCCCLK2
VEECLK2
2.2kΩ
2.2kΩ
10.4kΩ
Figure 8. CLK_SELECT Interface Schematic
50Ω
OUTP,
OUTN
Figure 9. OUTP and OUTN Interface Schematic
T/H
INP
INN
VEE
OUTP
OUTN
Figure 10. VEE Interface Schematic
T/H
VCCOF1, VCCOF2
OUTP
OUTN
VCCOB
Figure 11. VCCOF1, VCCOF2, and VCCOB Interface Schematic
T/H
INP
INN
VCCTHx
Figure 12. VCCTH1 and VCCTH2 Interface Schematic



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