TDA10045 datasheet(13/20 Pages) PHILIPS

13 / 20 page

2001 Nov 08

Philips Semiconductors

Product speciﬁcation

DVB-T channel receiver

TDA10045H

Tuner

• A RF tracking filter tracks the RF wanted frequency and

suppresses the image

• A first local wideband AGC is usually done at RF level,

the AGC level information could be provided externally

and the chip offers facilities to measure this level by the

optional ADC (this measurement is automatically made

by the DSP, the host has just to read the result)

• A mixer oscillator and a PLL downconverts the RF signal

to intermediate frequency IF1 (36.125 MHz typ.)

• SAW filters eliminate the power of the adjacent channels

around IF1.

IF interface

• It is either an analog IF amplifier when IF1 is sampled

(direct IF: digital downconversion concept) or an analog

IF amplifier followed by a downconversion from IF1 to

IF2 at a few MHz (e.g. 4.57 MHz)

• When this second solution is used, the ADC sampling

clock could be used (after low-pass filtering) as a

reference clock for downconversion (twice the ADC

sampling clock could also be provided)

• The IF amplifier is controlled by the digital AGC of the

chip. A simple RC circuit filters the single bit

(

∆Σ modulated) AGC control (VAGC)

• The sampling clock could also be used to control an

external ADC, the inputs to the chip will then be digital

(FI[9:0]).

TDA10045H

• The chip is controlled by an I2C-bus and driven by an

external low-cost crystal oscillator

• The software of the embedded DSP can be downloaded

from the main I2C-bus or from a dedicated I2C-bus

connected to an external slave I2C-bus EEPROM

• An internal bidirectional switch enables the tuner to be

programmed through the chip and then switch-off the

link in order to avoid phase noise distortions due to

I2C-bus traffic.

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