(Preliminary)

PL611s-16

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/06 Page 4

DC SPECIFICATIONS

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Supply Current, Dynamic, with

Loaded CMOS Outputs

@Vdd=3.3V, 27MHz,

load=15pF

4.0

mA

Supply Current, Dynamic, with

Loaded CMOS Outputs

@Vdd=2.5V, 27MHz,

load=15pF

2.7

mA

Supply Current, Dynamic with

Loaded CMOS Outputs

@Vdd=1.8V,27MHz,

load=5pF

1.2

mA

Operating Voltage

1.62

3.3

3.63

V

Output Low Voltage

0.4

V

Output High Voltage

V

Output Current, Low drive

4

mA

Output Current, Standard drive

8

mA

Output Current, High drive

16

mA

Short-circuit Current

±50

mA

PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION

The following guidelines are to assist you with a performance optimized PCB design:

- Keep all the PCB traces to PL611s-16 as short

as possible, as well as keeping all other traces

as far away from it as possible.

- When a reference input clock is generated from

a crystal (see diagram above), place the

PL611s-16 ‘FIN’ as close as possible to the

‘Xout’ crystal pin. This will reduce the cross-

talk between the reference input and the other

signals.

- Place the Loop Filter (LF) components as close

to the package pin of PL611s-16 as possible.

- Place a 0.01µF~0.1µF decoupling capacitor

between VDD and GND, on the component

side of the PCB, close to the VDD pin. It is not

recommended to place this component on the

backside of the PCB. Going through vias will

reduce the signal integrity, causing additional

jitter and phase noise.

- It is highly recommended to keep the VDD and

GND traces as short as possible.

- When connecting long traces (> 1 inch) to a

CMOS output, it is important to design the

traces as a transmission line or ‘stripline’, to

avoid reflections or ringing. In this case, the

CMOS output needs to be matched to the trace

impedance. Usually ‘striplines’ are designed

for 50Ω impedance and CMOS outputs usually

have lower than 50Ω impedance so matching

can be achieved by adding a resistor in series

with the CMOS output pin to the ‘stripline’

trace.

- Please contact PhaseLink for the application

note on how to design outputs driving long

traces or the Gerber files for the PL611s-16

layout.