1.8V-3.3V PicoPLL

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/04/07 Page 4

APPLICATION RECOMMENDATIONS FOR PL611s-17

PL611s-17 can accept a reference input >10kHz and produce a clock output in the MHz range, as shown in the

diagram ‘1’, below. Also, to save costs in consumer product system designs and for greater area optimization, it

is possible to use the XOUT of the RTC crystal (32.768KHz) as the reference input to the PL611s-17, as shown in

diagram ‘2’, below.

Diagram ‘1’

Diagram ‘2’

Note: An AC Coupling Cap may be required if RTC Clock amplitude is too small.

GUIDELINES FOR EXTERNAL COMPONENT SELECTION

For the optimum performance, an accurate external loop filter capacitor must be selected. A general guideline for

selecting this component based on the input frequency is shown in the table below.

Input Frequency

Capacitor Value

3MHz ~ 200MHz

1.0nF

300KHz ~ 10MHz

1.0nF

30KHz ~ 1.0MHz

4.7nF

10KHz ~ 100KHz

47nF

The optimal way to choose the value is using the following formula:

C(nF) = 0.8 + M/280

Where C = Loop Filter Capacitor value (in nF)

M = M counter value. Provided by PhaseLink with device samples.

Notes:

* Find the closest commercially available value. Values in the E12 range with 5% tolerance are acceptable.

* With possible M-counter values between 1 and 65536, the capacitor value is expected in the range 820pF thru

220nF.

32.768

KHz

C1

C2

ASIC

ASIC

ASIC

ASIC

XIN

XOUT

XIN

XOUT

REFIN

MHZ CLK

(Any Frequency)

1.8~3.3V

LF

LFGND

OE, PDB

FSEL, CLK1

1

2

3

6

5

4

REFIN

MHZ CLK

(Any Frequency)

1.8~3.3V

LF

LFGND

OE, PDB

FSEL, CLK1

1

2

3

6

5

4