1.8V to 3.3V PicoPLL

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LAYOUT RECOMMENDATIONS

DFN-6L Evaluation Board

The following guidelines are to assist you with a performance optimized PCB design:

Signal Integrity and Termination

Considerations

- Keep traces short!

- Trace = Inductor. With a capacitive load this equals

ringing!

- Long trace = Transmission Line. Without proper

termination this will cause reflections ( looks like ringing ).

- Design long traces as “striplines” or “microstrips” with

defined impedance.

- Match trace at one side to avoid reflections bouncing

back and forth.

Decoupling and Power Supply

Considerations

- Place decoupling capacitors as close as possible to the

VDD pin(s) to limit noise from the power supply

- Multiple VDD pins should be decoupled separately for

best performance.

- Addition of a ferrite bead in series with VDD can help

prevent noise from other board sources

- Value of decoupling capacitor is frequency dependant.

Typical values to use are 0.1µF for designs using crystals

< 50MHz and 0.01µF for designs using crystals > 50MHz.

Typical CMOS termination

Place Series Resistor as close as possible to CMOS output

CMOS Output Buffer

( Typical buffer impedance 20 Ω )

To CMOS Input

Series Resistor

Use value to match output

buffer impedance to 50 Ω

trace. Typical value 30 Ω

50Ω line